1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a test circuit for a semiconductor memory including an internally incorporated large scaled logic circuit.
2. Description of Related Art
Referring to FIG. 7, there is shown in a block diagram illustrating a general construction of the test circuit for the semiconductor memory including an internally incorporated large-scaled logic circuit. A semiconductor memory is generally designated with Reference Numeral 1 and includes a memory core 2, a large-scaled logic circuit 3, a test mode discriminating circuit 4 and a clock buffer 5, connected as shown. The semiconductor memory 1 also includes an input terminal 11 for a control signal or signals and data signals and an output terminal 12 for data signals, these terminals being connected to the large-scaled logic circuit 3. Furthermore, the semiconductor memory 1 includes an input terminal 41 for a test mode signal, which is connected to the test mode discriminating circuit 4, and an input terminal 51 for a clock signal, which is connected to the clock buffer 5. Reference Numeral 301 designates a bus for memory control signals and data signals outputted from the logic circuit 3 to the memory core 2, and Reference Numeral 302 denotes a bus for data signals outputted from the memory core 2 to the logic circuit 3. Reference Numeral 401 indicates a test signal line from the test mode discriminating circuit 4 to the logic circuit 3, and Reference Numeral 501 shows an internal clock signal line from the clock buffer 5 to the memory core 2 and the logic circuit 3.
Referring to FIG. 8, there is shown a circuit diagram showing a construction of the logic circuit 3 and a connection construction between the logic circuit 3 and the memory core 2 shown in FIG. 7, for illustrating a portion of the test circuit for the memory core. As shown in FIG. 8, the memory core 2 and the logic circuit 3 are operated in synchronism with a rising edge of the clock signal 501.
In order to write to the memory core 2, data to be written is generated in an internal logic circuit 31 of the logic circuit 3 or supplied through the control signal and data signal input terminal 11 from an external of the semiconductor memory 1, and also supplied through a buffer 23 and the memory control signal and data signal bus 301 to the memory core 2.
On the other hand, read-out data is outputted from a buffer 22 of the memory core 2 to the data signal output bus 302, and latched in a data latch 32 in synchronism with for example the rising edge of the internal clock signal 501 so that it is supplied to the internal logic circuit 31.
The data supplied to the internal logic circuit 31 is processed in the internal logic circuit 31 or outputted through the data output terminal 12 to the external of the semiconductor memory.
In the prior art, in order to test the memory core in the semiconductor memory mentioned above, the writing and reading of the memory core 2 are performed by elevating the frequency of the internal clock signal of the internal clock line 501 as shown in FIG. 6, and the data read out from the memory core 2 is compared with an expected value by the internal logic circuit 31, or alternatively, the data read out from the memory core 2 is outputted to an external of the semiconductor memory so that the pass/fail of operation is discriminated by a testing system.
In the above mentioned prior art, however, the following problems have been encountered.
A first problem is that in the operation at the high frequency as shown in the timing chart of FIG. 6 it is difficult to locate or identify a defective portion when the data read out from the memory core 2 is not consistent with the expected value.
Because, the cause for the defective operation in the high frequency operation can be classified to three, namely,
(1) the inside of the memory core 2; PA1 (2) the internal logic circuit 31; and PA1 (3) a signal delay between the memory core 2 and the logic circuit 3.
However, it is impossible to determine one among the three probable causes, by only the frequency dependency.
A second problem is that in order to separate the third cause (3) in connection with the first problem as mentioned above, it is necessary to previously prepare the buffer 22 having a large driving capability so that the signal delay is made sufficiently small.
However, since the memory core 2 consumes a large current as one macro cell, it is actually impossible to prepare the buffer 22 having a large driving capability similar to that of the buffer 23 of the internal logic circuit 31, from the viewpoint of a power consumption.